1. Field of the Invention
This invention relates to a field effect transistor using a Group III-V compound semiconductor and more particularly to a field effect transistor fit for the configuration of a logic circuit.
In the recent data processing field, devices which are capable of faster logic motions have been in demand. The feasibility of substituting field effect transistors using compound semiconductors (such as, for example, GaAs) for the silicon devices has been under study.
In the case of compound semiconductor devices (such as, for example, microwave grade field effect transistors and HEMT) which are used in amplifiers as in portable telephones, further integration of logic parts necessitates logic grade field effect transistors using a compound semiconductor.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional field effect transistor using a compound semiconductor; part A represents a plane view and part B represents a cross section taken through part A along the line XX--XX.
In the diagram, 101 denotes a compound semiconductor layer which, in the illustrated case, is formed of semi-insulating GaAs. Incidentally, the compound semiconductor layer 101 refers at times to what is formed on a substrate made of a compound semiconductor and at other times to what constitutes itself a compound semiconductor substrate. Numeral 102 denotes a well region which has incorporated a p type impurity therein. Numeral 103 is denotes a channel region which has incorporated an n type impurity therein. Numeral 104 is an LDD region which has incorporated an n type impurity therein at a higher concentration than in the channel region. 105 is denotes a source region and 106 denotes a drain region, which both have incorporated an n type impurity therein at a higher concentration than the LDD region 104. 107 is a source electrode and 108 is a drain electrode, which both are ohmically connected respectively to the source and the drain region. 109 is a gate electrode which is kept in Schottky contact with the upper side of the channel region 103.
As is clear from FIG. 1A, the gate electrode 109 is provided with a projecting part 109a. This projecting part 109a is furnished for this transistor for the following reason. Between the source and the drain electrode 107 and 108, the compound semiconductor layer (semi-insulating GaAs layer) 101 along or outside the boundaries of these regions has formed therein a fine channel through which carriers are travelling, thus generating a short channel effect besides the channel region 103 containing an n type impurity. The projecting part 109a formed by extending the gate electrode 109 onto the compound semiconductor layer 101, therefore, is expected to exert a gate field on the carriers travelling through the fine channel and consequently suppress the generation of the short channel effect.
The gate electrode 109 is further provided with a gate pad part 109b, to which are connected necessary wires.
The well region 102 has a conductivity opposite to that of the channel region 103 and, due to the pn junction thereof with the channel region 103, serves to preclude the possibility of carriers leaking from the channel region 103 to the compound semiconductor layer 101 and reducing the short channel effect.
The field effect transistor which is formed of such compound semiconductors as mentioned above promises to find utility in high-speed arithmetic operations because the speed of travel of carriers in the crystal is markedly high as compared with a silicon device.
The field effect transistor using compound semiconductors, though capable of high-speed operations as mentioned above, has the problem of suffering the static properties thereof to vary particularly at a low frequency.
Specifically, this transistor induces dispersion in drain current, transconductance, and drain conductance in a low frequency zone and, as a result, disperses the point of change of the transistor operation (the timing for the high-low or the low-high change). This dispersion is called as "delay variation."
This problem is especially serious in the logic circuit. This is because the elements forming the logic circuit cannot execute logical operations with expected accuracy unless the point of change mentioned above is constant. Usually, the delay variation is allayed by enlarging the timing margin of the logical operations. This measure results in exerting an extra timing margin on the circuit operations and consequently posing the problem of preventing the field effect transistor using compound semiconductors from fulfilling the inherent property, namely high-speed operations.
This delay variation is a phenomenon that is peculiar to the use of a compound semiconductor. The delay variation in fact does not occur when crystals made of a single element are used as in the silicon devices. The addition of the margin in due respect of the delay variation to the design of a logical circuit is a problem that is peculiar to the field effect transistor using compound semiconductors.